Precharge system in a SRAM

ABSTRACT

A precharge system of the divided bit line types for a SRAM (Static Random Access Memory) reduces the active current consumption and bit line peak current by decreasing the number of bit lines to be precharged at any one time during a precharge cycle. For this, the system has a block selection signal generator that responds to certain column addresses with a block selection signal. A sub-block selection signal generator responds to certain addresses among the remaining column addresses with a sub-block selection signal. A precharge decoder responds to pulses from the pulse generator and the block selection signal with a block selection precharge signal. A divided bit line precharge decoder responds to the sub-block selection signal and block selection precharge signal with a pulse for precharging only a certain sub-block of a certain block of the array of memory cells of the SRAM. A column predecoder responds to the block and sub-block selection signals with a block selecting pulse, and a column decoder responds to the block selecting pulse and the remaining column addresses to connect certain bit lines of the sub-block with a data line. The advantages of this are to reduce the power consumption of such a SRAM chip, and the noise in its power supply voltage, by precharging of only a portion of the whole number of bit lines at any one time.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor memory devices and, moreparticularly, to a precharge system of the divided bit line method in aStatic Random Access Memory (hereinafter SRAM).

Development is well underway of SRAM devices having high density, highspeed and low power consumption. High speed and low active currentconsumption can be obtained by employing an address transition detectionmethod in the bit line precharge circuit of a SRAM. However, a highdensity of memory cells increases the number of bit lines to be soprecharged and, thus, the active current, and creates a problem from thebit line peak current. That is, the charging current in a prechargingcycle on the long and large capacitance bit lines that result from thehigh density takes so great a portion of the active current of the totalchip that the peak current of the bit lines then causes fluctuations inVcc and Vss that have a bad influence on the stability of operation.Consequently, the total and peak precharging current for the bit linesshould be reduced for stable operation of the chip.

A method for reducing the power consumption in a conventional SRAMprecharges every bit line in sequentially selected blocks (i.e., theparts of the memory cell array respectively controlled by the wordlines) as described in IEEE Journal of Solid-State Circuits, Vol. 20,No. 5, Oct. 1985, pp 941. However, with this method, the reduction ofthe active current consumption is limited by the large number of bitlines in each block of a high density SRAM.

SUMMARY OF THE INVENTION

Therefore, it is the principal object of this invention to provide a bitline precharge system that reduces the active current consumption andbit line peak current by decreasing the number of bit lines to beprecharged at one time during the precharge cycle, sufficiently even fora high density SRAM.

BRIEF DESCRIPTION OF THE DRAWING

The novel features believed characteristic of the invention, as well asother features and advantages thereof, will best be understood byreference to the following detailed description of a particularembodiment, read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of the particular embodiment;

FIG. 2 is an electrical schematic of a memory cell array portion theembodiment of FIG. 1;

FIGS. 3A and 3B are circuit diagrams of address buffer portions of theembodiment of FIG. 1;

FIG. 4 is a circuit diagram of a bit line selector portion of theembodiment of FIG. 1;

FIG. 5 is a circuit diagram of block selector and precharge decoderportions of the embodiment of FIG. 1;

FIG. 6 is a circuit diagram of a divided bit line precharge decoderportion of the embodiment of FIG. 1; and

FIG. 7 is a circuit diagram of a portion of a sub-block portion of thememory cell array of FIG. 2.

DETAILED DESCRIPTION OF THE PARTICULAR EMBODIMENT

FIG. 1 is a block diagram of the divided bit line precharge system ofthe invention in a SRAM embodiment. For convenience of explanation, itis assumed that the SRAM of FIG. 1 is a 256K memory chip which isdivided into four corresponding large-scale blocks or memory cell arraysLBL₁ -LBL₄. Each large-scale block has 512 memory cells (130 in FIG. 7)along the row direction and 128 memory cells along the column direction,for a total of 65,566 memory cells in each lock LBL₁ -LBL₄.

Representative large-scale block LBL₁, as shown in FIG. 2, has its 128columns (128 pairs of bit lines) divided into eight blocks BL₁ -BL₈ ofsixteen columns, and each of the blocks BL₁ -BL₈ divided into foursub-blocks (SBL₁ -SBL₄ for block BL₁) of four columns. Therefore, eachsub-block SBL₁ -SBL₄ is composed of four pairs of bit lines. Also, oneend of each of the 128 pairs of bit lines of the large-scale block isconnected to a precharge circuit 18a, and the other end is connected toa column decoder 19a which can select said bit line pair. Large scaleblocks LBL₂ -LBL₃ have the same structure as that of large-scale blockLBL₁ of FIG. 2.

As shown in FIG. 1, the row (word line WL_(1-WL) ₅₁₂ in FIG. 7) of thememory cells is selected by nine row address input signals XA₃ -XA₈ andXA₁₂ -XA₁₄ from row address input pins (not shown) on the externalprocessor of the 256K SRAM chip. The row address signals XA₃ -XA₈ andXA₁₂ -XA₁₄ are applied to a row address buffer 10a which changes the rowaddress signals from TTL level into CMOS logic level row address signalsA₃ -A₈, A₁₂ -A₁₄ and their inverted signals A₃ -A₈, A_(12-A) ₁₄. Theseare decoded in a known row predecoder 16 and known row decoders 17a, 17bto select the word-line row.

Column address signals XA₀, XA₁, XA₂, XA₉, XA₁₀ and XA₁₁ from columnaddress input pins (not shown) are changed into CMOS logic level byaddress buffers 10b, 10c and 10d. Signals XA₉ and XA₁₁ select one of thefour large-scale blocks LBL₁ -LBL₄, signals XA₁ and XA₂ select onesub-block of the sub-blocks SBL₁ -SBL₄ in the one selected large-scaleblock, and XA₀ and XA₁₀ select a pair of the four pairs of bit lines inthe one selected sub-block.

Column address signals XA₉, XA₁₁ and XA₁, XA₂ are changed into CMOSlogic level signals A₉, A₁₁ and A₁, and A₂ and their inverted signalsA₉, A₁₁ and A₁ A₂ in buffers 10b, 10c, respectively, but signals XA₀ andXA₁₀ are converted into CMOS logic level in address buffer 10d connectedcolumn decoders 19a-19d.

Block selector 13, as later described with respect to FIG. 5, iscomposed of gates that receive the address signals A₉, A₁₁ and A₉, A₁₁as inputed from the address buffer 10b and generate a block selectionsignal LBS₁ (i.e. LBS₁, LBS₂, LBS₃ or LBS₄) that can select one of thelarge-scale blocks LBL₁ -LBL₄. Bit line selector 14, as later describedwith reference to FIG. 4, is a logic circuit that similarly generates asub-block selection signal SBSi (i.e. SBS₁, SBS₂, SBS₃ or SBS₄) from theaddress signals A₁, A₂ and A₁, A₂ of the address buffer 10c.

An address transition detector (not shown) in pulse generator 11 detectsa variation of one of the row address signals A₃ -A₈, A₁₂ -A₁₄ from therow address buffer 10a, and in response, the pulse generator 11generates a short pulse O P X B. Although short, the pulse O P X B fromthe pulse generator has enough width to precharge the address-signalselected bit line before the enabling of the word line. The pulsegenerator 11 can be that of Patent Appln. No. 86-11077, for example.

Precharge decoder 12, as later described with reference to FIG. 5, is alogic circuit that responds to the pulse O P X B from the pulsegenerator 11 by generating a pulse O P X B I which precharges certainbit lines in the large-scale block of the large-scale blocks LBL₁ -LBL₄selected by the block selection signal LBSi from the block selector 13.

Divided bit line precharge decoder 15, as later described with referenceto FIG. 6, is composed of logic gate circuits that then generate a pulseO P X B i ' which precharges one of the sub-blocks SBL₁ -SBL₄ in eachblock BL₁ -BL₈ in the selected large-scale block with the pulse O P X Bi from the precharge decoder 12, the one sub-block being selected by thesub-block selection signal SBSi from the bit line selector 14.

For the latter, a column predecoder 21, a portion 110 of which is laterdescribed with reference to FIG. 7, generates address signals whichselect the one selected sub-block of the sub-blocks SBL₁ -SBL₄ in alleight blocks BL₁ -BL₈ (FIG. 2) in the selected one of the large-scaleblocks LBL₁ -LBL₄. For this, the column predecoder receives thesub-block selection signal SBSi of the bit line selector 14 and theblock selection signal LBSi of the block selector 13.

The large-scale blocks LBL₁ -LBL₄ are respectively associated with thecolumn decoders 19a-19d, a portion 120 of which is later described withreference to FIG. 7. The column decoder associated with the selectedblock then generates a bit-line selection signal that selects one of thepairs of bit lines in the selected sub-block from address signals A₀,A₁₀ and their inverted signals A₀, A₁₀ from the address buffer 10d.

The large-scale blocks LBL₁ -LBL₄ are also respectively associated withprecharge circuits 18a-18d, a portion 140 of which is later describedwith reference to FIG. 7. The precharge circuits 18a-18d are connectedwith one end of each pair of bit lines in the respective large-scaleblocks. They are well known circuits for precharging the bit linesbefore the word line is enabled during a read or write cycle.

FIG. 3A and FIG. 3B are the circuit diagrams of the address buffers10a-10d. The address buffer 10c of FIG. 1 uses address buffer circuitsof the type shown in FIG. 3A and the address buffers 10a, 10b and 10duse address buffer circuits of type shown in FIG. 3B for the columnaddress signals (hereinafter sometimes generically XAi, XAj) thereof.

The address buffer circuits of FIG. 3A and FIG. 3B each include NORgates 42, 42', respectively. These respond to a chip select signal C Sfrom an input pin (not shown) and the respective column address signalsXAi, XAj. They comprise an inverter composed of a pair of PMOStransistors and a pair of NMOS transistors 30, 31 and 32, 33 and 30',31', and 32', 33', respectively.

The PMOS transistors 30, 31 and 30', 31' are connected serially and theNMOS transistors 32, 33 and 32', 33', are connected in parallel. Theparallel-connected NMOS transistors 32, 33 and 32', 33' are respectivelyconnected to the drains of the PMOS transistors 31, 31' and output lines43, 43'. Power supply voltage Vcc is applied to the sources of the PMOStransistors 30, 30', and the sources of the parallel-connected NMOStransistors 32, 33 and 32', 33' are grounded. Address input signals XAi,XAj are respectively applied to the gates of the PMOS transistors 31,31' and NMOS transistors 32, 32'. The chip selection signal C S isapplied to the gates of PMOS transistors 30, 30' and NMOS transistors33, 33' for enabling operation when in a low state (hereinafter, a 0state).

When so enabled, the operation of the above-described SRAM starts whenthe column address signals XAi and XAj change from a high state(hereinafter, a 1 state) to a 0 state. Voltages on the output lines 43,43' then go to a 1 state.

In the column address buffer (10c) according to FIG. 3A, the output line43 is connected to inputs of inverters 46 and 48. These inverters eachcomprise a PMOS transistor 34, 38, respectively. The source of each PMOStransistor is connected to the power supply voltage Vcc and the drain,to the drain of an NMOS transistor 35, 39, respectively, and an outputline. The source of the NMOS transistor of each inverter is grounded.The gates of the PMOS and NMOS transistors are the inverter inputs thatare connected to the output line 43. The output line of the inverter 46is connected to the input of another, corresponding inverter 47 of PMOSand NMOS transistors 36, 37. The output lines of inverters 47, 48 thusprovide the address signals (i.e., A_(i) =A₁, A₂ and A_(j) =A₁, A₂).

The circuits for the column address buffers (10a, 10b, 10d) according toFIG. 3B are the same as those of FIG. 3A, with corresponding componentscorrespondingly referenced and, therefore, not described again, exceptthat still another, corresponding inverter 49 is connected betweenoutput line 43' and a node 45 that is the input of inverters 46', 48'.

Therefore, when the address buffer 10c (FIG. 1) according to FIG. 3Aoperates and its address-signal input XAi goes to a 0 state, A_(i) andA_(i) go to a 1 state and a 0 state, respectively. When XA_(j) =0 inaddress buffer 10a, 10b or 10d according to FIG. 3B, however, A_(j) andA_(j) go to 0 and 1 states, respectively.

Referring to FIG. 4, which is a detailed circuit diagram of the bit lineselector 14 of FIG. 1, its input signals A₁, A₁, A₂, A₂, which are hereshown to on lines 50-53, are the output signals of the address buffer10c of circuits as shown in FIG. 3A from the column address inputsignals XA₁, XA₂ (FIG. 1), as stated above. Lines 50-53 are connected inpair combinations to inputs of four input NAND gates 58a-58d. Each NANDgate 58a-58d comprises a pair of PMOS transistors 54, 55 with sourcesconnected to a common power supply voltage Vcc. The common-connecteddrains of each PMOS transistor pair 54, 55, which act as the output, areconnected with the drain of respective NMOS transistors 56. The sourcesof the NMOS transistors 56 are respectively connected with the drains ofNMOS transistor 57, the sources of which are grounded. The gates of thePMOS transistors 54 and NMOS transistors 56 are connected in common asthe respective input to the NAND gates 58a-58d from the lines 50 and 51,and the gates of the PMOS transistors 55 and NMOS transistors 57 areconnected in the as inputs common to the NAND gates 58a-58d from thelines 52 and 53.

Therefore, when both of the column address signals XA₁ and XA₂ (FIG. 1)are 0 states, only sub-block selection signal SBS₄ goes to a 0 state.When column address signal XA₁ is a 1 state and, XA₂ is a 0 state, onlysignal SBS₃ goes to a 0 state. When column address signal XA₁ is a 0state and, XA₂ is a 1 state, only signal SBS₂ goes to a 0 state. Andwhen both column address signals XA₁ and XA₂ are 1 states, only signalSBS₁ goes to a 0 state.

FIG. 5 is a detailed circuit diagram of the block selector 13 andprecharge decoder 12 of FIG. 1.

As stated above with reference to FIG. 1 and shown in FIG. 5, blockselector 13 accepts the output signals A₉, A₉, A₁₁, A₁₁ of the addressbuffer 10b (FIG. 1), which has the circuit structure of FIG. 3B, hereshown on lines 63, 63', 64, 64'. NOR gates 73a-73d, which have the samestructure as the NAND gates 58a-58d of FIG. 4, except for thedrawing-indicated inverters, are connected in pair combinations to thelines 63, 63', 64, 64'. The outputs of the NOR gates 73a-73d arerespectively connected to inverters 74a-74d, which are, in turn,respectively connected to output lines 65-68 to provide the blockselection signals LBS₁ -LBS₄.

The precharge decoder 12 receives the block selection signals LBS₁₋ LBS₄on the output lines 65-68 in respective NOR gates 75a-75d. Each NOR gatealso receives the pulse O P X B, which is the output of the pulsegenerator 11 (FIG. 1). The outputs of the NOR gates 75a-75d are appliedto inverters 76a-76d, respectively, which complete the precharge decoder12 and provide its block-precharge-output pulses O P X B₁, O P X B₂, O PX B₃ and O P X B₄ along lines 69-72, respectively.

Therefore, when column address signals XA₉ and XA₁₁ (FIG. 1) are in 0states, only block selection signal LBS₄ and pulse O P X B₄ are in 0states. When, XA₉ and XA₁₁ in a 0 state and a 1 state, respectively,only LBS₃ and O P X B₃ are in 0 states. When, XA₉ and XA₁₁ are in a 1state and a 0 state, respectively, only LBS₂ and O P X B₂ are in 0states. And when both XA₉ and XA₁₁ are in 1 states, only LBS₁ and O P XB₁ are in 0 states.

FIG. 6 is a detailed circuit diagram of the divided bit line prechargedecoder 15 of FIG. 1. The sub-block selection signals SBS₁ -SBS₄, whichare the output signals of the bit line selector 14 (FIGS. 1 and 4), areapplied on lines 59-62 (FIGS. 4 and 6). Each of four NOR gates 84a-84d,which are same as those of FIG. 5, is connected between respective onesof the lines 59-62 and the line 69-72 (FIG. 5), which carry theprecharge pulses O P X B₁, O P X B₂, O P X B₃ and O P X B₄, and aregenerically designated line 90 for pulse O P X Bi in FIG. 6. For theprecharge pulse O P X B₁ line 90 (i.e., line 69 of FIG. 5) is alsoconnected to the gate of an equalization transistor (133 in FIG. 7) ofblock LBL₁ in the precharge circuit 18a (FIG. 1), as described laterwith reference to FIG. 7. In the same way, for pulses O P X B₂ , O P XB₃ and O P X B₄, respectively, line 90 is connected to the gates ofequalization transistors of blocks LBL₂, LBL₃, LBL₄, respectively.

The output lines 91-94 of the NOR gates 84a-84d are respectivelyconnected to the inputs of inverters 85a-85d, which provide theprecharge pulses O P X B₁ ', O P X B₂ ', O P X B₃ ', O P X B₄ ' on theiroutput lines 86-89, respectively. The output lines 86-89 are connectedto each of the sub-block precharge circuits 18a-18d (FIG. 1) of thelarge-scale blocks LBL₁ -LBL₄, respectively. This is shown, for example,for block LBL₁ (FIGS. 1 and 2) in FIG. 2.

FIG. 7 is the detailed circuit diagram for sub-block SBL₁ (FIG. 2) inblock BL₁ (FIG. 2) of large-scale block LBL₁ (FIGS. 1 and 2), which is,of course, representative of the others. The corresponding portion 110(FIGS. 2 and 7) of the column predecoder 21 (FIGS. 1 and 2) is alsoshown in FIG. 7. It is composed of input NAND gates 111a-111d whichaccept one signal (LBS₁ on line 117e in FIGS. 5 and 7) among the blockselection signals LBS₁ -LBS₄ (LBS_(i) in FIG. 1) and the sub-blockselection signals SBS₁ -SBS₄ (SBS_(i) in FIG. 1) on lines 59-62 (FIGS. 4and 7) as its inputs. There are a total of eight such column predecoderportions 110 for large-scale block LBL₁, one for each block BL₁ -BL₈ inthe block LBL₁. The NAND gates 111a-111d have the same structures asthose if FIG. 4. The output signals SBS₁ ', SBS₂ ', SBS₃ ' and SBS₄ ' ofthe column predecoder portion 110 are connected, respectively, to theinputs of corresponding portions 120 (only one for output line 113 shownin FIG. 7) of the column decoder 19a (FIGS. 1 and 2) for sub-blocks SBL₁-SBL₄ of block BL₁ in the block LBL₁ (FIGS. 1 and 2).

The column decoder portion 120 shown in FIG. 7 comprises fourthree-input NAND gates 121a-121d, each of which is the same as those ofFIG. 4, with the addition of a third, common-source-connected PMOStransistor 54' and a third, serial, source-to-drain connected NMOStransistor NMOS transistor 57' to accept the third input, signal SBS₁ 'on output line 113, in addition to respective pair combinations of theaddress signals A₀, A₁₀, A₀, A₁₀ from the address buffer circuit 10d.The output lines 122a-122d of the four input NAND gates 121a-121d areconnected to the gates of respective pairs of isolation transistors131a-131d, 132a-132d, which are respectively connected serially acrossone end of the four pairs of bit lines BL, B L (only one eachreferenced) of the sub-blocks SBL₁ of the blocks BL₁ -BL₈ in large-scaleblock LBL₁ (FIG. 2) Therefore, there are a total of 32 column decoders120 in large-scale block LBL₁.

The other ends of the four pairs of bit lines of the sub-blocks of theblocks of the large-scale blocks LBL₁ -LBL₄ are respectively connectedto precharge circuits 18a-18_(d) (FIG. 1), details of specific portions140a-140d of which for precharge circuit 18a for one sub-block SBL₁ ofone block BL₁ of large-scale block LBL₁ are shown in FIG. 7. As shownfor portion 140a, each portion has two pairs of parallel-connected PMOStransistors 134, 135 and 136, 137, the sources of which are connected incommon to the power supply voltage Vcc and the drains of which areconnected in common to the bit lines BL and B L. The gate of one PMOStransistor 134, 137 of each pair is grounded, and gate of the other PMOStransistor 135, 136 is connected to line 89 (from FIG. 6) to provide thepulse O P X B₁ '.

Memory cells 130 and a PMOS equalization transistor 133 are placedacross each pair of the bit lines BL and B L. Word lines WL_(1-WL) ₅₁₂from the corresponding row decoder 17a (FIG. 1) are connected to thememory cells 130. Pulse O P X B₁ ' is applied to the gates of the PMOSequalization transistors 133 along line 89 (FIG. 6) to equalize eachpair of the bit lines.

From now on, the detailed operation of the invention will be explained.It is assumed that, due to a change of address, column address signalsXA₁ =XA₂ =0 and XA₉ =XA₁₀ =XA₁₁ =1, the signals from address buffers 10band 10d (FIG. 1), which have the structure shown in FIG. 3B, A₀ =A₉ =A₁₀=A₁₁ =1, A₀ =A₉ =A₁₀ =A₁₁ =0 are and the signal from address buffer 10 c(FIG. 1), which has the structure shown in FIG. 3A, are A₁ =A₀, A₁ =A₂=1.

Because both signals A₉ and A₁₁ are in 0 states, only output signal LBS₁(FIGS. 1, 5 and 7) of the block selector 13 on line 117e (FIGS. 5 and 7)goes to a 0 state. In addition, only the output pulse O P X B₁ on line69 of the precharge decoder 12 in FIG. 5 goes to a 0 state. In bit lineselector 14 of FIG. 4, only SBS₁ goes to 0 state, because A₁ =A₂ =0.Because SBS₁ =O P X B₁ =0 in the divided bit line precharge decoder 15of FIG. 6, the output of NOR gate 84d goes to a 1 state and onlyinverter 85d goes to a 0 state and provides O P X B₁ '=0 along line 89.In addition, as shown in FIG. 7, because only O P X B₁ is in a 0 state,sub-block precharge circuits 140a-140d of sub-blocks SBL₁ of blocks BL₁-BL.sub. 8 in FIG. 2 are enabled.

As further shown in FIG. 7, the conduction of the PMOS transistors 135,136 in the precharge circuits 140a-140d, both of each pair of the bitlines BL and B L are precharged to the power supply voltage Vcc, andthrough the conduction of equalization transistor 133 because O P X B₁'=0, both of the bit lines BL and B L have the same voltage level Vcc.

As may be determined from FIG. 2, therefore, this reduces the currentconsumption in the precharging cycle by precharging only 1/4 of totalpairs of bit lines, and reduce the peak current by preventing an abruptflow of large current, again because only sub-blocks SBL₁ of large-scaleblock LBL₁ are precharged.

On the other hand, during the read cycle, a certain word line is enabledby the selection of row predecoder 16 and row decoder 17a so that avoltage difference between bit lines BL and B L is developed after saidprecharge operation. Since the inputs of column decoder are A₀ =A₁₀ =1,the column decoder 120 of FIG. 7 begins to operate.

In this case, the output SBS₁ of NAND gate 111a goes to 1 due to LBS₁ =0as described in detail before. Since A₀ =A₁₀ =1 and the output line 122aof the input NAND gate 121a goes to 0, the isolation transistors 131aand 132a are turned on. Therefore, the voltage difference between saidbit lines BL and B L propagates along the data lines DL and D L, and isamplified in a sense amplifier (not shown) and applied on theinput-output bus line (not shown).

As described in detail before, owing to the precharging of only aportion of whole bit lines, it is possible to reduce the powerconsumption of the chip, and the noise in Vcc by alleviation of Vccswing due to peak current.

Although the invention has been described with reference to theprecharging of only 1/4 of the total bit lines in sub-block SBS₁, itwill become apparent to persons skilled in the art that the powerconsumption can be reduced by 1/8 or 1/16 using 3 or 4 column addresses.

Various modifications of the disclosed embodiment, as well as otherembodiments of the invention, will become apparent to persons skilled inthe art upon reference to the description of the invention. It istherefore contemplated that the appended claims will cover any suchmodifications or embodiments as fall within the true scope of theinvention.

What is claimed is:
 1. A precharge system for precharging a portion of aplurality of bit lines in an array of memory cells arranged in a matrixof rows and columns, said precharge system comprising:a memory cellarray arranged in a matrix of rows and columns to define a plurality oflarge-scale blocks of said memory cell array, each large-scale blockhaving a plurality of sub-blocks, each sub-block having at least onepair of bit lines; precharging means for precharging said bit lines ofsaid sub-blocks of said memory cell array; and selection means selectingone of said sub-blocks for said precharging means to precharge said bitlines thereof.
 2. A precharge system as claimed in claim 1, wherein saidselection means comprises a divided bit line precharge decoder forproducing a signal to precharge said one selected sub-block and a columndecoder for producing a signal to select a pair of said bit lines insaid one selected sub-block, each sub-block having at least two pairs ofsaid bit lines.